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| 56F803 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F803 Rev. 16 09/2007 freescale.com Document Revision History Version History Rev. 16 Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: "However, the high pulse width does not have to be any particular percent of the low pulse width." 56F803 General Description * * * * Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K x 16-bit words (64KB) Program Flash 512 x 16-bit words (1KB) Program RAM 4K x 16-bit words (8KB) Data Flash 2K x 16-bit words (4KB) Data RAM 2K x 16-bit words (4KB) Boot Flash Up to 64K x 16-bit words each of external Program and Data memory * * * * * * * * * * 6-channel PWM module Two 4-channel 12-bit ADCs Quadrature Decoder CAN 2.0 B module Serial Communication Interface (SCI) Serial Peripheral Interface (SPI) Up to two General Purpose Quad Timers JTAG/OnCETM port for debugging 16 shared GPIO lines 100-pin LQFP package * * * * * * 6 3 3 PWM Outputs Current Sense Inputs Fault Inputs PWMA RESET IRQA EXTBOOT IRQB 6 JTAG/ OnCE Port VCAPC VDD 2 6 VSS 6* Digital Reg Analog Reg VDDA VSSA 4 4 A/D1 A/D2 VREF ADC Interrupt Controller Low Voltage Supervisor 4 Quadrature Decoder 0 / Quad Timer A Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit Program Memory 32252 x 16 Flash 512 x 16 SRAM Quad Timer B Quad Timer C Quad Timer D 2 CAN 2.0A/B 2 2 SCI or GPIO COP/ Watchdog Data Memory 4096 x 16 Flash 2048 x 16 SRAM Boot Flash 2048 x 16 Flash * PAB * * PDB * * * * IPBB CONTROLS 16 PLL CLKO XDB2 CGDB XAB1 XAB2 16-Bit 56800 Core XTAL Clock Gen EXTAL * INTERRUPT CONTROLS 16 COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] 4 SPI or GPIO Application-Specific Memory & Peripherals IPBus Bridge (IPBB) External Bus Interface Unit External Address Bus Switch External Data Bus Switch Bus Control A[00:05] 6 10 16 PS Select DS Select WR Enable RD Enable A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 D[00:15] 56F803 Block Diagram *includes TCS pin which is reserved for factory use and is tied to VSS 56F803 Technical Data, Rev. 16 Freescale Semiconductor 3 Part 1 Overview 1.1 56F803 Features 1.1.1 * * * * * * * * * * * * * * Processing Core Efficient 16-bit 56800 family controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique processor addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface 1.1.2 * * Memory Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution -- 31.5K x 16-bit words of Program Flash -- 512K x 16-bit words of Program RAM -- 4K x 16-bit words of Data Flash -- 2K x 16-bit words of Data RAM -- 2K x 16-bit words of Boot Flash * Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states -- As much as 64K x 16 bits of Data memory -- As much as 64K x 16 bits of Program memory 1.1.3 * Peripheral Circuits for 56F803 Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes, supports Freescale's patented dead time distortion correction Two 12-bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and PWM modules can be synchronized Quadrature Decoder with four inputs (shares pins with Quad Timer) * * 56F803 Technical Data, Rev. 16 4 Freescale Semiconductor 56F803 Description * * * * * * * * * * Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins CAN 2.0 B module with 2-pin ports for transmit and receive Serial Communication Interface (SCI) with two pins (or two additional GPIO lines) Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines) Computer Operating Properly (COP) Watchdog timer Two dedicated external interrupt pins Sixteen multiplexed General Purpose I/O (GPIO) pins External reset input pin for hardware reset JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock 1.1.4 * * * * Energy Information Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available 1.2 56F803 Description The 56F803 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact device and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F803 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable 56F803 Technical Data, Rev. 16 Freescale Semiconductor 5 software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal outputs (the module is also capable of supporting three independent PWM functions, for a total of six PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard opto-isolators. A "smoke-inhibit", write-once protection feature for key parameters and patented PWM waveform distortion correction circuit are also provided. The PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM module provides a reference output to synchronize the ADC. The 56F803 incorporates a separate Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include a Serial Communications Interface (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIO) if that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller are also included on the 56F803. 1.3 State of the Art Development Environment * * Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 56F803 Technical Data, Rev. 16 6 Freescale Semiconductor Product Documentation 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F803. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: www.freescale.com Table 1-1 56F803 Chip Documentation Topic 56800E Family Manual DSP56F801/803/805/807 User's Manual 56F803 Technical Data Sheet 56F803 Errata Description Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56F801, 56F803, 56F803, and 56F807 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number 56800EFM DSP56F801-7UM DSP56F803 DSP56F803E 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL "asserted" "deasserted" Examples: 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-17, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Power (VDD or VDDA) Ground (VSS or VSSA) Supply Capacitors PLL and Clock Address Bus1 Data Bus Bus Control Interrupt and Program Control Pulse Width Modulator (PWM) Port Serial Peripheral Interface (SPI) Port1 Quadrature Decoder Port2 Serial Communications Interface (SCI) Port1 CAN Port Analog to Digital Converter (ADC) Port Quad Timer Module Port JTAG/On-Chip Emulation (OnCE) 1. Alternately, GPIO pins 2. Alternately, Quad Timer pins Number of Pins 7 7 2 3 16 16 4 4 12 4 4 2 2 9 2 6 Detailed Description Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 56F803 Technical Data, Rev. 16 8 Freescale Semiconductor Introduction Power Port Ground Port Power Port Ground Port VDD VSS VDDA VSSA 6 6* 1 1 6 3 2 3 PWMA0-5 ISA0-2 FAULTA0-2 PWMA Port Other Supply Ports PLL and Clock VCAPC EXTAL XTAL CLKO 1 1 1 1 6 2 8 1 1 1 SCLK (GPIOE4) MOSI (GPIOE5) MISO (GPIOE6) SS (GPIOE7) SPI Port or GPIO 56F803 A0-A5 External Address Bus or GPIO A6-7 (GPIOE2-E3) A8-15 (GPIOA0-A7) External Data Bus D0-D15 16 1 1 TXD0 (GPIOE0) RXD0 (GPIOE1) SCI0 Port or GPIO PS External Bus Control DS RD WR 1 1 1 1 8 1 1 1 1 1 1 MSCAN_RX MSCAN_TX CAN 1 ANA0-7 VREF ADCA Port PHASEA0 (TA0) Quadrature Decoder or Quad Timer A PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3) TCK TMS JTAG/OnCETM Port TDI TDO TRST DE 2 1 1 1 1 1 1 1 1 1 1 TD1-2 Quad Timer D IRQA IRQB RESET EXTBOOT Interrupt/ Program Control *includes TCS pin which is reserved for factory use and is tied to VSS Figure 2-1 56F803 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parenthesis. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 9 2.2 Power and Ground Signals Table 2-2 Power Inputs No. of Pins 6 1 Signal Name VDD VDDA Signal Description Power--These pins provide power to the internal structures of the chip, and should all be attached to VDD. Analog Power--This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply. Table 2-3 Grounds No. of Pins 5 1 1 Signal Name VSS VSSA TCS Signal Description GND--These pins provide grounding for the internal structures of the chip, and should all be attached to VSS. Analog Ground--This pin supplies an analog ground. TCS--This Schmitt pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS. Table 2-4 Supply Capacitors No. of Pins 2 Signal Name VCAPC Signal Type Supply State During Reset Supply Signal Description VCAPC--Connect each pin to a 2.2 F or greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, please refer to Section 5.2. 56F803 Technical Data, Rev. 16 10 Freescale Semiconductor Clock and Phase Locked Loop Signals 2.3 Clock and Phase Locked Loop Signals Table 2-5 PLL and Clock No. of Pins 1 Signal Name EXTAL Signal Type Input State During Reset Input Signal Description External Crystal Oscillator Input--This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. Crystal Oscillator Output--This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more information, please refer to Section 3.5.3. 1 CLKO Output Chip-driven Clock Output--This pin outputs a buffered clock signal. By programming the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user can select between outputting a version of the signal applied to XTAL and a version of the device's master clock at the output of the PLL. The clock frequency on this pin can also be disabled by programming the CLKOSEL[4:0] bits in CLKOSR. 1 XTAL Input/ Output Chip-driven 2.4 Address, Data, and Bus Control Signals Table 2-6 Address Bus Signals No. of Pins 6 2 Signal Name A0-A5 A6-A7 Signal Type Output Output State During Reset Tri-stated Tri-stated Signal Description Address Bus--A0-A5 specify the address for external Program or Data memory accesses. Address Bus--A6-A7 specify the address for external Program or Data memory accesses. Port E GPIO--These two pins are General Purpose I/O (GPIO) pins that can be individually programmed as input or output pins. After reset, the default state is Address Bus. 8 A8-A15 Output Tri-stated Address Bus--A8-A15 specify the address for external Program or Data memory accesses. Port A GPIO--These eight pins are General Purpose I/O (GPIO) pins that can be individually programmed as input or output pins. After reset, the default state is Address Bus. GPIOE2- GPIOE3 Input/O utput Input GPIOA0- GPIOA7 Input/O utput Input 56F803 Technical Data, Rev. 16 Freescale Semiconductor 11 Table 2-7 Data Bus Signals No. of Pins 16 Signal Name D0-D15 Signal Type Input/O utput State During Reset Tri-stated Signal Description Data Bus-- D0-D15 specify the data for external Program or Data memory accesses. D0-D15 are tri-stated when the external bus is inactive. Internal pull-ups may be active. Table 2-8 Bus Control Signals No. of Pins 1 1 1 Signal Name PS DS WR Signal Type Output Output Output State During Reset Tri-stated Tri-stated Tri-stated Signal Description Program Memory Select--PS is asserted low for external Program memory access. Data Memory Select--DS is asserted low for external Data memory access. Write Enable--WR is asserted during external memory write cycles. When WR is asserted low, pins D0-D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. Read Enable--RD is asserted during external memory read cycles. When RD is asserted low, pins D0-D15 become inputs and an external device is enabled onto the device data bus. When RD is deasserted high, the external data is latched inside the controller. When RD is asserted, it qualifies the A0-A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. 1 RD Output Tri-stated 2.5 Interrupt and Program Control Signals Table 2-9 Interrupt and Program Control Signals No. of Pins 1 Signal Name IRQA Signal Type Input (Schmitt) State During Reset Input Signal Description External Interrupt Request A--The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge- triggered. External Interrupt Request B--The IRQB input is an external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. 1 IRQB Input (Schmitt) Input 56F803 Technical Data, Rev. 16 12 Freescale Semiconductor Pulse Width Modulator (PWM) Signals Table 2-9 Interrupt and Program Control Signals (Continued) No. of Pins 1 Signal Name RESET Signal Type Input (Schmitt) State During Reset Input Signal Description Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure a complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. 1 EXTBOOT Input (Schmitt) Input External Boot--This input is tied to VDD to force device to boot from off-chip memory. Otherwise, it is tied to VSS. 2.6 Pulse Width Modulator (PWM) Signals Table 2-10 Pulse Width Modulator (PWMA) Signals No. of Pins 6 3 Signal Name PWMA0-5 ISA0-2 Signal Type Output Input (Schmitt) State During Reset Tri-stated Input Signal Description PWMA0-5-- These are six PWMA output pins. ISA0-2-- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA. FAULTA0-2-- These three fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. 3 FAULTA0-2 Input (Schmitt) Input 56F803 Technical Data, Rev. 16 Freescale Semiconductor 13 2.7 Serial Peripheral Interface (SPI) Signals Table 2-11 Serial Peripheral Interface (SPI) Signals No. of Pins 1 Signal Name MISO Signal Type Input/Out put State During Reset Input Signal Description SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high impedance state if the slave device is not selected. Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is MISO. 1 MOSI Input/Out put Input SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is MOSI. 1 SCLK Input/Out put Input SPI Serial Clock--In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is SCLK. 1 SS Input Input SPI Slave Select--In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is SS. GPIOE6 Input/Out put Input GPIOE5 Input/Out put Input GPIOE4 Input/Out put Input GPIOE7 Input/Out put Input 56F803 Technical Data, Rev. 16 14 Freescale Semiconductor Quadrature Decoder Signals 2.8 Quadrature Decoder Signals Table 2-12 Quadrature Decoder (Quad Dec0) Signals No. of Pins 1 Signal Name PHASEA0 TA0 1 PHASEB0 TA1 1 INDEX0 TA2 1 HOME0 TA3 Signal Type Input Input/Output Input Input/Output Input Input/Output Input Input/Output State During Reset Input Input Input Input Input Input Input Input Signal Description Phase A--Quadrature Decoder #0 PHASEA input TA0--Timer A Channel 0 Phase B--Quadrature Decoder #0 PHASEB input TA1--Timer A Channel 1 Index--Quadrature Decoder #0 INDEX input TA2--Timer A Channel 2 Home--Quadrature Decoder #0 HOME input TA3--Timer A Channel 3 2.9 Serial Communications Interface (SCI) Signals Table 2-13 Serial Communications Interface (SCI0) Signals No. of Pins 1 Signal Name TXD0 GPIOE0 Signal Type Output Input/Output State During Reset Input Input Signal Description Transmit Data (TXD0)--SCI0 transmit data output Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. 1 RXD0 GPIOE1 Input Input/Output Input Input Receive Data (RXD0)-- SCI0 receive data input Port E GPIO--This General Purpose I/O (GPIO) pin can be individually programmed as an input or output pin. After reset, the default state is SCI input. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 15 2.10 CAN Signals Table 2-14 CAN Module Signals No. of Pins 1 1 Signal Name MSCAN_ RX MSCAN_ TX Signal Type Input (Schmitt) Output State During Reset Input Output Signal Description MSCAN Receive Data--This is the MSCAN input. This pin has an internal pull-up resistor. MSCAN Transmit Data--MSCAN output. CAN output is open-drain output and a pull-up resistor is needed. 2.11 Analog-to-Digital Converter (ADC) Signals Table 2-15 Analog to Digital Converter Signals No. of Pins 4 4 1 Signal Name ANA0-3 ANA4-7 VREF Signal Type Input Input Input State During Reset Input Input Input Signal Description ANA0-3--Analog inputs to ADC channel 1 ANA4-7--Analog inputs to ADC channel 2 VREF--Analog reference voltage for ADC. Must be set to VDDA-0.3V for optimal performance. 2.12 Quad Timer Module Signals Table 2-16 Quad Timer Module Signals No. of Pins 2 Signal Name TD1-2 Signal Type Input/Output State During Reset Input Signal Description TD1-2-- Timer D Channel 1-2 56F803 Technical Data, Rev. 16 16 Freescale Semiconductor JTAG/OnCE 2.13 JTAG/OnCE Table 2-17 JTAG/On-Chip Emulation (OnCE) Signals No. of Pins 1 Signal Name TCK Signal Type State During Reset Signal Description Input Input, pulled low Test Clock Input--This input pin provides a gated clock to synchronize the (Schmitt) internally test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. Input (Schmitt) Input, pulled high internally Test Mode Select Input--This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: Always tie the TMS pin to VDD through a 2.2K resistor. 1 TMS 1 TDI Input (Schmitt) Output Input, pulled high internally Tri-stated Test Data Input--This input pin provides a serial input data stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Test Data Output--This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. Test Reset--As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted at power-up and whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. 1 TDO 1 TRST Input (Schmitt) Input, pulled high internally 1 DE Output Output Debug Event--DE provides a low pulse on recognized debug events. Part 3 Specifications 3.1 General Characteristics The 56F803 is fabricated in high-density CMOS with 5-V tolerant TTL-compatible digital inputs. The term "5-V tolerant" refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 17 Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56F803 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 3-1 Absolute Maximum Ratings Characteristic Supply voltage All other input voltages, excluding Analog inputs Voltage difference VDD to VDDA Voltage difference VSS to VSSA Analog inputs ANA0-7 and VREF Analog inputs EXTAL and XTAL Current drain per pin excluding VDD, VSS, PWM outputs, TCS, VPP, VDDA, VSSA Symbol VDD VIN VDD VSS VIN VIN I Min VSS - 0.3 VSS - 0.3 - 0.3 - 0.3 VSSA- 0.3 VSSA- 0.3 -- Max VSS + 4.0 VSS + 5.5V 0.3 0.3 VDDA+ 0.3 VSSA+ 3.0 10 Unit V V V V V V mA Table 3-2 Recommended Operating Conditions Characteristic Supply voltage, digital Supply Voltage, analog Voltage difference VDD to VDDA Symbol VDD VDDA VDD Min 3.0 3.0 -0.1 Typ 3.3 3.3 Max 3.6 3.6 0.1 Unit V V V 56F803 Technical Data, Rev. 16 18 Freescale Semiconductor General Characteristics Table 3-2 Recommended Operating Conditions Characteristic Voltage difference VSS to VSSA ADC reference voltage Ambient operating temperature Symbol VSS VREF TA Min -0.1 2.7 -40 Typ - - Max 0.1 VDDA 85 Unit V V C Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol 100-pin LQFP Unit Notes Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to case Junction to center of case I/O pin power dissipation Power dissipation Junction to center of case Four layer board (2s2p) RJA RJMA RJMA (2s2p) RJMA RJC JT P I/O PD PDMAX 41.7 C/W 2 37.2 34.2 C/W C/W 2 1,2 Four layer board (2s2p) 32 10.2 0.8 User Determined P D = (IDD x VDD + P I/O) (TJ - TA) /RJA C/W C/W C/W W W W 1,2 3 4, 5 7 Notes: 1. 2. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. Junction to ambient thermal resistance, Theta-JA (RJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where "s" is the number of signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. Junction to case thermal resistance, Theta-JC (RJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 3. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 19 4. Thermal Characterization Parameter, Psi-JT (JT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. JT is a useful value to use to estimate junction temperature in steady state customer environments. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 5. 6. 7. See Section 5.1 from more details on thermal design considerations. TJ = Junction Temperature TA = Ambient Temperature 3.2 DC Electrical Characteristic Table 3-4 DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage (Schmitt trigger inputs)1 Input low voltage (Schmitt trigger inputs)1 Input high voltage (all other digital inputs) Input low voltage (all other digital inputs) Input current high (pullup/pulldown resistors disabled, VIN=VDD) Input current low (pullup/pulldown resistors disabled, VIN=VSS) Input current high (with pullup resistor, VIN=VDD) Input current low (with pullup resistor, VIN=VSS) Input current high (with pulldown resistor, VIN=VDD) Input current low (with pulldown resistor, VIN=VSS) Nominal pullup or pulldown resistor value Output tri-state current low Output tri-state current high Symbol VIHC VILC VIHS VILS VIH VIL IIH Min 2.25 0 2.2 -0.3 2.0 -0.3 -1 Typ -- -- -- -- -- -- -- Max 2.75 0.5 5.5 0.8 5.5 0.8 1 Unit V V V V V V A IIL -1 -- 1 A IIHPU IILPU IIHPD IILPD RPU, RPD IOZL IOZH -1 -210 20 -1 -- -- -- -- 30 1 -50 180 1 A A A A K -10 -10 -- -- 10 10 A A 56F803 Technical Data, Rev. 16 20 Freescale Semiconductor DC Electrical Characteristic Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Input current high (analog inputs, VIN=VDDA)2 Input current low (analog inputs, VIN=VSSA)2 Output High Voltage (at IOH) Output Low Voltage (at IOL) Output source current Output sink current PWM pin output source current3 PWM pin output sink current4 Input capacitance Output capacitance VDD supply current Run 6 Wait7 Stop Low Voltage Interrupt, external power supply8 Low Voltage Interrupt, internal power supply9 Power on Reset10 1. Symbol IIHA IILA VOH VOL IOH IOL IOHP IOLP CIN COUT IDDT5 Min -15 -15 VDD - 0.7 -- 4 4 10 16 -- -- Typ -- -- -- -- -- -- -- -- 8 12 Max 15 15 -- 0.4 -- -- -- -- -- -- Unit A A V V mA mA mA mA pF pF -- -- -- VEIO VEIC VPOR 2.4 2.0 -- 126 105 60 2.7 2.2 1.7 152 129 84 3.0 2.4 2.0 mA mA mA V V V 1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS, TDI, and MSCAN_RX 2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 3. PWM pin output source current measured with 50% duty cycle. 4. PWM pin output sink current measured with 50% duty cycle. 5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL enabled. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 21 8. This low-voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V). 10. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally regulated voltage is typically 100mV less than VDD during ramp-up, until 2.5V is reached, at which time it self-regulates. 180 IDD Digital IDD Analog IDD Total 150 120 IDD (mA) 90 60 30 0 20 40 Freq. (MHz) 60 80 Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14) 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown. 56F803 Technical Data, Rev. 16 22 Freescale Semiconductor Flash Memory Characteristics VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH - VIL)/2. Low High 90% 50% 10% VIL Rise Time Figure 3-2 Input Signal Measurement References Figure 3-3 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data Active Data3 Valid Data3 Figure 3-3 Signal States 3.4 Flash Memory Characteristics Table 3-5 Flash Memory Truth Table Mode Standby Read Word Program Page Erase Mass Erase XE1 L H H H H YE2 L H H L L SE3 L H L L L OE4 L H L L L PROG5 L L H L L ERASE6 L L L H H MAS17 L L L L H NVSTR8 L L H H H 1. X address enable, all rows are disabled when XE = 0 2. Y address enable, YMUX is disabled when YE = 0 3. Sense amplifier enable 4. Output enable, tri-state Flash data out bus when OE = 0 56F803 Technical Data, Rev. 16 Freescale Semiconductor 23 5. Defines program cycle 6. Defines erase cycle 7. Defines mass erase cycle, erase whole block 8. Defines non-volatile store cycle Table 3-6 IFREN Truth Table Mode Read Word program Page erase Mass erase IFREN = 1 Read information block Program information block Erase information block Erase both block IFREN = 0 Read main memory block Program main memory block Erase main memory block Erase main memory block Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF Characteristic Program time Erase time Mass erase time Endurance1 Data Retention1 Symbol Min 20 20 100 10,000 10 Typ - - - 20,000 30 Max - - - - - Unit us ms ms cycles years Figure Figure 3-4 Figure 3-5 Figure 3-6 Tprog* Terase* Tme* ECYC DRET The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time Tnv* - 5 - us Figure 3-4, Figure 3-5, Figure 3-6 Figure 3-4, Figure 3-5 Figure 3-6 Figure 3-4 Figure 3-4, Figure 3-5, Figure 3-6 NVSTR hold time NVSTR hold time (mass erase) NVSTR to program set up time Recovery time Tnvh* Tnvh1* Tpgs* Trcv* - - - - 5 100 10 1 - - - - us us us us 56F803 Technical Data, Rev. 16 24 Freescale Semiconductor Flash Memory Characteristics Table 3-7 Flash Timing Parameters (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF Characteristic Cumulative program HV period2 Program hold time3 Address/data set up time3 Address/data hold time3 Symbol Min - Typ 3 Max - Unit ms Figure Figure 3-4 Thv Tpgh Tads Tadh - - - - - - - - - Figure 3-4 Figure 3-4 Figure 3-4 1. One cycle is equal to an erase program and read. 2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs NVSTR Tpgs Thv Tnvh Trcv Tprog Tpgh Figure 3-4 Flash Program Cycle 56F803 Technical Data, Rev. 16 Freescale Semiconductor 25 IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 3-5 Flash Erase Cycle IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-6 Flash Mass Erase Cycle 56F803 Technical Data, Rev. 16 26 Freescale Semiconductor External Clock Operation 3.5 External Clock Operation The 56F803 system clock can be derived from an external crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.5.1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 3-9. In Figure 3-7 a recommended crystal oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-8 no external load capacitors should be used. The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: CL1 * CL2 CL = CL1 + CL2 + Cs = 12 + 12 12 * 12 + 3 = 6 + 3 = 9pF This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit. EXTAL XTAL Rz fc Recommended External Crystal Parameters: Rz = 1 to 3 M fc = 8MHz (optimized for 8MHz) Figure 3-7 Connecting to a Crystal Oscillator 56F803 Technical Data, Rev. 16 Freescale Semiconductor 27 3.5.2 Ceramic Resonator It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is shown. Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-7 no external load capacitors should be used. EXTAL XTAL Rz fc Recommended Ceramic Resonator Parameters: Rz = 1 to 3 M fc = 8MHz (optimized for 8MHz) Figure 3-8 Connecting a Ceramic Resonator Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). 3.5.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-9. The external clock source is connected to XTAL and the EXTAL pin is grounded. 56F803 XTAL EXTAL External Clock VSS Figure 3-9 Connecting an External Clock Signal 56F803 Technical Data, Rev. 16 28 Freescale Semiconductor External Clock Operation Table 3-8 External Clock Operation Timing Requirements3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Frequency of operation (external clock driver)1 Clock Pulse Width2, 3 Symbol fosc tPW Min 0 6.25 Typ -- -- Max 80 -- Unit MHz ns 1. See Figure 3-9 for details on using the recommended connection of an external clock driver. 2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. However, the high pulse width does not have to be any particular percent of the low pulse width. 3. Parameters listed are guaranteed by design. VIH External Clock 90% 50% 10% tPW tPW 90% 50% 10% VIL Note: The midpoint is VIL + (VIH - VIL)/2. Figure 3-10 External Clock Timing 56F803 Technical Data, Rev. 16 Freescale Semiconductor 29 3.5.4 Phase Locked Loop Timing Table 3-9 PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Symbol fosc fout/2 tplls tplls Min 4 40 -- -- Typ 8 -- 1 100 Max 10 110 10 200 Unit MHz MHz ms ms External reference crystal frequency for the PLL1 PLL output frequency 2 PLL stabilization time 3 0o to +85oC PLL stabilization time3 -40o to 0oC 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the User Manual. ZCLK = fop 3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation. 3.6 External Bus Asynchronous Timing Table 3-10 External Bus Asynchronous Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Address Valid to WR Asserted WR Width Asserted Wait states = 0 Wait states > 0 WR Asserted to D0-D15 Out Valid Data Out Hold Time from WR Deasserted Data Out Set Up Time to WR Deasserted Wait states = 0 Wait states > 0 RD Deasserted to Address Not Valid Address Valid to RD Deasserted Wait states = 0 Wait states > 0 Symbol tAWR tWR 7.5 (T*WS) + 7.5 tWRD tDOH tDOS 2.2 (T*WS) + 6.4 tRDA tARDD 18.7 (T*WS) + 18.7 0 -- -- -- -- ns ns ns ns ns -- 4.8 -- -- 4.2 -- ns ns ns ns Min 6.5 Max -- Unit ns 56F803 Technical Data, Rev. 16 30 Freescale Semiconductor External Bus Asynchronous Timing Table 3-10 External Bus Asynchronous Timing1, 2 (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Input Data Hold to RD Deasserted RD Assertion Width Wait states = 0 Wait states > 0 Address Valid to Input Data Valid Wait states = 0 Wait states > 0 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted Symbol tDRD tRD 19 (T*WS) + 19 tAD -- -- tARDA tRDD -- -- tWRRD tRDRD tWRWR tRDWR 6.8 0 14.1 12.8 2.4 (T*WS) + 2.4 -- -- -- -- ns ns ns ns ns ns -4.4 1 (T*WS) + 1 -- ns ns ns -- -- ns ns Min 0 Max -- Unit ns 56F803 Technical Data, Rev. 16 Freescale Semiconductor 31 1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.5) A0-A15, PS, DS (See Note) tARDA tARDD tRDA tRDRD RD tAWR tWRWR tWR tWRRD tRD tRDWR WR tWRD tDOS tAD tDOH tRDD tDRD D0-D15 Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 3-11 External Bus Asynchronous Timing 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 RESET De-assertion to First External Address Output Symbol tRAZ tRA 275,000T 128T tRDA 33T -- -- 34T ns ns ns Figure 3-12 Min -- Max 21 Unit ns See Figure Figure 3-12 Figure 3-12 56F803 Technical Data, Rev. 16 32 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF Characteristic Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 IRQA Width Assertion to Recover from Stop State4 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Symbol tIRW tIDM Min 1.5T 15T Max -- -- Unit ns ns See Figure Figure 3-13 Figure 3-14 tIG 16T -- ns Figure 3-14 tIRI tIW tIF 13T 2T -- -- ns ns Figure 3-15 Figure 3-16 Figure 3-16 -- -- tIRQ 275,000T 12T ns ns Figure 3-17 -- -- tII -- -- 275,000T 12T ns ns Figure 3-17 275,000T 12T ns ns 1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns. 2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: * After power-on reset * When recovering from Stop state 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 33 RESET tRA tRAZ tRDA A0-A15, D0-D15 PS, DS, RD, WR First Fetch First Fetch Figure 3-12 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive) 56F803 Technical Data, Rev. 16 34 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing A0-A15, PS, DS, RD, WR IRQA, IRQB First Interrupt Instruction Execution tIDM a) First Interrupt Instruction Execution General Purpose I/O Pin IRQA, IRQB tIG b) General Purpose I/O Figure 3-14 External Level-Sensitive Interrupt Timing IRQA, IRQB tIRI A0-A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-15 Interrupt from Wait State Timing tIW IRQA tIF A0-A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing 56F803 Technical Data, Rev. 16 Freescale Semiconductor 35 tIRQ IRQA tII A0-A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service 3.8 Serial Peripheral Interface (SPI) Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Symbol tC 50 25 tELD -- 25 tELG -- 100 tCH 17.6 12.5 tCL 24.1 25 tDS 20 0 tDH 0 2 tA 4.8 tD 3.7 15.2 ns 15 ns Figure 3-21 -- -- ns ns -- -- ns ns -- -- ns ns -- -- -- -- ns ns ns ns Figures 3-18, , 3-20, 3-21 Figures 3-18, , 3-20, 3-21 Figures 3-18, , 3-20, 3-21 Figures 3-18, , 3-20, 3-21 Figure 3-21 -- -- ns ns Figure 3-21 -- -- ns ns Min Max Unit See Figure Figures 3-18, , 3-20, 3-21 Figure 3-21 Table 3-12 SPI Timing1 56F803 Technical Data, Rev. 16 36 Freescale Semiconductor Serial Peripheral Interface (SPI) Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Table 3-12 SPI Timing1 Symbol tDV -- -- tDI 0 0 tR -- -- tF -- -- Min Max 4.5 20.4 -- -- 11.5 10.0 9.7 9.0 Unit ns ns ns ns ns ns ns ns See Figure Figures 3-18, , 3-20, 3-21 Figures 3-18, , 3-20, 3-21 Figures 3-18, , 3-20, 3-21 Figures 3-18, , 3-20, 3-21 SS (Input) SS is held High on master tC tR tF SCLK (CPOL = 0) (Output) tCL tCH tCL tF tR SCLK (CPOL = 1) (Output) tDS tDH tCH MISO (Input) MSB in tDI Bits 14-1 tDV LSB in tDI(ref) MOSI (Output) Master MSB out tF Bits 14-1 Master LSB out tR Figure 3-18 SPI Master Timing (CPHA = 0) 56F803 Technical Data, Rev. 16 Freescale Semiconductor 37 SS (Input) tC SS is held High on master tF tCL tR SCLK (CPOL = 0) (Output) tCH tCL tF SCLK (CPOL = 1) (Output) tCH tR tDS tDH MISO (Input) tDV(ref) MSB in tDI Bits 14-1 tDV LSB in MOSI (Output) Master MSB out tF Bits 14- 1 Master LSB out tR Figure 3-19 SPI Master Timing (CPHA = 1) 56F803 Technical Data, Rev. 16 38 Freescale Semiconductor Serial Peripheral Interface (SPI) Timing SS (Input) tC tCL tF tR tELG SCLK (CPOL = 0) (Input) tELD tCH tCL SCLK (CPOL = 1) (Input) tA tCH tR tF tD MISO (Output) tDS Slave MSB out Bits 14-1 tDV tDH Slave LSB out tDI tDI MOSI (Input) MSB in Bits 14-1 LSB in Figure 3-20 SPI Slave Timing (CPHA = 0) 56F803 Technical Data, Rev. 16 Freescale Semiconductor 39 SS (Input) tC tCL tR tF SCLK (CPOL = 0) (Input) tELD tCH tCL tELG SCLK (CPOL = 1) (Input) tDV tA tCH tF tR tD MISO (Output) tDS Slave MSB out Bits 14-1 tDV tDH Slave LSB out tDI MOSI (Input) MSB in Bits 14-1 LSB in Figure 3-21 SPI Slave Timing (CPHA = 1) 3.9 Quad Timer Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Timer input period Timer input high/low period Timer output period Symbol PIN PINHL POUT Min 4T+6 2T+3 2T Max -- -- -- Unit ns ns ns Table 3-13 Timer Timing1, 2 56F803 Technical Data, Rev. 16 40 Freescale Semiconductor Quadrature Decoder Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Timer output high/low period 1. Table 3-13 Timer Timing1, 2 POUTHL 1T -- ns In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 3-22 Timer Timing 3.10 Quadrature Decoder Timing Table 3-14 Quadrature Decoder Timing1,2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Quadrature input period Quadrature input high/low period Quadrature phase period Symbol PIN PHL PPH Min 8T+12 4T+6 2T+3 Max -- -- -- Unit ns ns ns 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12. ns. VSS = 0 V, VDD = 3.0 - 3.6V, TA = -40 to +85C, CL 50pF. 2. Parameters listed are guaranteed by design. 56F803 Technical Data, Rev. 16 Freescale Semiconductor 41 PPH PPH PPH PPH Phase A (Input) PIN PHL PHL Phase B (Input) PIN PHL PHL Figure 3-23 Quadrature Decoder Timing 3.11 Serial Communication Interface (SCI) Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width Symbol BR RXDPW TXDPW Min -- 0.965/BR 0.965/BR Max (fMAX*2.5)/(80) 1.04/BR 1.04/BR Unit Mbps ns ns Table 3-15 SCI Timing4 1. fMAX is the frequency of operation of the system clock in MHz. 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 3-24 RXD Pulse Width 56F803 Technical Data, Rev. 16 42 Freescale Semiconductor Analog-to-Digital Converter (ADC) Characteristics TXD SCI receive data pin (Input) TXDPW Figure 3-25 TXD Pulse Width 3.12 Analog-to-Digital Converter (ADC) Characteristics Table 3-16 ADC Characteristics Characteristic ADC input voltages Resolution Integral Non-Linearity3 Differential Non-Linearity Monotonicity ADC internal clock5 Conversion range Power-up time Conversion time Sample time Input capacitance Gain Error (transfer gain)5 Offset Voltage5 Total Harmonic Distortion5 Signal-to-Noise plus Distortion5 Effective Number of Bits5 Spurious Free Dynamic Range5 Bandwidth fADIC RAD tADPU tADC tADS CADI EGAIN VOFFSET THD SINAD ENOB SFDR BW 0.5 VSSA -- -- -- -- 0.95 -80 60 55 9 65 -- Symbol VADCIN RES INL DNL Min 01 12 -- -- Typ -- -- +/- 2.5 +/- 0.9 GUARANTEED -- -- 16 6 1 5 1.00 -15 64 60 10 70 100 5 VDDA -- -- -- -- 1.10 +20 -- -- -- -- -- MHz V tAIC cycles6 tAIC cycles6 tAIC cycles6 pF6 -- mV dB dB bit dB KHz Max VREF2 12 +/- 4 +/- 1 Unit V Bits LSB4 LSB4 56F803 Technical Data, Rev. 16 Freescale Semiconductor 43 Table 3-16 ADC Characteristics Characteristic ADC Quiescent Current (both ADCs) VREF Quiescent Current (both ADCs) Symbol IADC IVREF Min -- -- Typ 50 12 Max -- 16.5 Unit mA mA 1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital output code of 0. 2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VDDA-0.3V. 3. Measured in 10-90% range. 4. LSB = Least Significant Bit. 5. Guaranteed by characterization. 6. tAIC = 1/fADIC ADC analog input 3 1 2 4 1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf) 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf) 3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms) 4. Sampling capacitor at the sample and hold circuit. (1pf) Figure 3-26 Equivalent Analog Input Circuit 3.13 Controller Area Network (CAN) Timing Table 3-17 CAN Timing2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40x to +85xC, CL 50pF, MSCAN Clock = 30MHz Characteristic Baud Rate Bus Wakeup detection 1 Symbol BRCAN T WAKEUP Min -- 5 Max 1 -- Unit Mbps s 56F803 Technical Data, Rev. 16 44 Freescale Semiconductor Controller Area Network (CAN) Timing 1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event (on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The value of 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps. 2. Parameters listed are guaranteed by design. MSCAN_RX CAN receive data pin (Input) T WAKEUP Figure 3-27 Bus Wakeup Detection 56F803 Technical Data, Rev. 16 Freescale Semiconductor 45 3.14 JTAG Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic TCK frequency of operation2 TCK cycle time TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Symbol fOP tCY tPW tDS tDH tDV tTS tTRST tDE Min DC 100 50 0.4 1.2 -- -- 50 4T Max 10 -- -- -- -- 26.6 23.5 -- -- Unit MHz ns ns ns ns ns ns ns ns Table 3-18 JTAG Timing1, 3 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW VIH tPW VM TCK (Input) VM = VIL + (VIH - VIL)/2 VM VIL Figure 3-28 Test Clock Input Timing Diagram 56F803 Technical Data, Rev. 16 46 Freescale Semiconductor JTAG Timing TCK (Input) tDS tDH TDI TMS (Input) TDO (Output) Input Data Valid tDV Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-29 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-30 TRST Timing Diagram DE tDE Figure 3-31 OnCE--Debug Event 56F803 Technical Data, Rev. 16 Freescale Semiconductor 47 Part 4 Packaging 4.1 Package and Pin-Out Information 56F803 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F803. D9 D8 D7 D6 D5 D4 D3 VSS VDD D2 D1 D0 VCAPC SCLK MOSI MISO SS TD2 TD1 CLKO DE RESET EXTBOOT RXD0 TXD0 D10 D11 D12 D13 D14 D15 A0 VDD VSS A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 VDD PS DS PIN 76 PIN 1 ORIENTATION MARK PIN 51 PIN 26 PWMA5 PWMA4 PWMA3 PWMA2 PWMA1 PWMA0 HOME0 INDEX0 VSS VDD PHASEB0 PHASEA0 VSS VDD VDD VDDA VSSA EXTAL XTAL AN7 AN6 AN5 AN4 AN3 AN2 48 A14 A15 VSS WR RD IRQA IRQB TCS TCK TMS TDI TDO TRST VCAPC ISA0 ISA1 ISA2 FAULTA0 MSCAN_TX FAULTA1 MSCAN_RX FAULTA2 VREF AN0 AN1 Figure 4-1 Top View, 56F803 100-pin LQFP Package 56F803 Technical Data, Rev. 16 Freescale Semiconductor Package and Pin-Out Information 56F803 Table 4-1 56F803 Pin Identification By Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name D10 D11 D12 D13 D14 D15 A0 VDD VSS A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 VDD PS DS Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name A14 A15 VSS WR RD IRQA IRQB TCS TCK TMS TDI TDO TRST VCAPC ISA0 ISA1 ISA2 FAULTA0 MSCAN_TX FAULTA1 MSCAN_RX FAULTA2 VREF AN0 AN1 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name AN2 AN3 AN4 AN5 AN6 AN7 XTAL EXTAL VSSA VDDA VDD VDD VSS PHASEA0 PHASEB0 VDD VSS INDEX0 HOME0 PWMA0 PWMA1 PWMA2 PWMA3 PWMA4 PWMA5 Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name TXD0 RXD0 EXTBOOT RESET DE CLKO TD1 TD2 SS MISO MOSI SCLK VCAPC D0 D1 D2 VDD VSS D3 D4 D5 D6 D7 D8 D9 56F803 Technical Data, Rev. 16 Freescale Semiconductor 49 S 0.15 (0.006) S AC T-U -TNOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.070 (0.003). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS DIM MIN MAX A 13.950 14.050 B 13.950 14.050 C 1.400 1.600 D 0.170 0.270 E 1.350 1.450 F 0.170 0.230 G 0.500 BSC H 0.050 0.150 J 0.090 0.200 K 0.500 0.700 M 12 REF N 0.090 0.160 Q 1 5 R 0.150 0.250 S 15.950 16.050 V 15.950 16.050 W 0.200 REF X 1.000 REF INCHES MIN MAX 0.549 0.553 0.549 0.553 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 1 5 0.006 0.010 0.628 0.632 0.628 0.632 0.008 REF 0.039 REF S Z S S T-U S AC Z -ZB -UA 0.15 (0.006) S AB T-U S 9 Z S AE AD -AB-AC96X G 0.100 (0.004) AC (24X PER SIDE) SEATING PLANE AE M R D F N J C E 0.25 (0.010) GAUGE PLANE H W K X DETAIL AD Q 0.20 (0.008) M AC T-U SECTION AE-AE S 0.15 (0.006) S AC Z V 0.15 (0.006) S S T-U S Z S Figure 4-2 100-pin LQPF Mechanical Information 56F803 Technical Data, Rev. 16 50 Freescale Semiconductor Thermal Design Considerations Please see www.freescale.com for the most current case outline. Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: TJ = T A + ( P D x RJA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: RJA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation 56F803 Technical Data, Rev. 16 Freescale Semiconductor 51 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56F803 Rev. 16 09/2007 |
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